The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to a multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks.
Synchronous Dynamic Random Access Memory (SDRAM) memory devices provide enhanced performance over their asynchronous predecessors and generally enable improved read/write access time through the interleaving of data across multiple memory cell blocks such that one block may be accessed while another is being refreshed. Follow-on Double Data Rate (DDR) SDRAM effectively doubles data transfer rates by transferring data on both the rising and falling edges of the device clock.
In Double Data Rate Two (DDR2) devices, the external data bus is clocked at twice the speed of the memory cells enabling four words of data to be transferred per memory cell cycle. Therefore, without speeding up the operation of the memory cells themselves, DDR2 devices can effectively operate at twice the bus speed of DDR memories. In comparison, Double Data Rate Three (DDR3) devices enable their input/output (I/O) bus to run at four times the speed of the memory cells while providing lower power consumption, higher bandwidth but greater latency than comparable DDR2 memory devices.
Current DDR3 memory devices have eight banks of memory and the package pinout places all of the I/O pads to one side of the chip/package. Since each I/O path must reach all eight of these banks, some of these paths are relatively long while others are comparatively short. These disparate signal path lengths lead to difficult timing issues. A conventional approach directed towards ameliorating this problem is to place ‘half banks’ on each side of device chip so that I/O paths on the left and right sides of the device are not shared. However, this approach then doubles the number of column decoders required and places some of these column decodes farther away from the I/O pads.